FEATURES

• All designs are synchronous to a single system clock
  
• All critical inputs feature digital filtering for noise immunity
  
• All designs are parametric and may be customized by user
  
• All designs made in VHDL and are portable across device families and vendors
  

In an FPGA a designer can design an SOPC, incorporating all digital functions on a single chip resulting in a highly compact and sturdy design. The entire design can be synchronized with a single global clock resulting in highly reliable performance over a wide range of oscillator frequencies and temperatures. The product will have a low component count and power consumption, smaller and simpler PCBs design and fewer connectors. Synchronization problems associated propagation delays of discrete devices are eliminated. Noise problems due to excessive connections, difficult supply and ground routing, coupling of switching signals to adjacent tracks and PCB layers are eliminated. Debugging is simpler, duration of the design cycle and cost are greatly reduced cos