Associated with CDAC-ATC, Mumbai.
IP Cores >> Peripheral
IP Cores
 
DSP
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FEATURES

  • All designs are synchronous to a single system clock
  • All critical inputs feature digital filtering for noise immunity
  • All designs are parametric and may be customized by user
  • All designs made in VHDL and are portable across device families and vendors

SNO DESCRIPTION
PER1 PARALLEL A to D INTERFACE CONTROLLER
PER2 LED DISPLAY CONTROLLER
PER3 MATRIX KEYBOARD CONTROLLER
PER4 PRIORITY INTERRUPT CONTROLLER
PER5 REAL TIME CLOCK AND CALENDAR
PER6 SERIAL FLASH INTERFACE CONTROLLER