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COURSE A23: LOGIC FOR INTERFACING PORTS AND PERIPHERALS TO A CPU
USES
All microprocessor based products containing peripheral ICs such as interrupt controller,
UART, RTCC, counters, A to D converters, D to A converters, programmable ports,
memory, disks, addon cards, etc
PREREQUISITES
Course-A1. Introduction to VHDL and VLSI design (I)
CONTENTS
- What is meant by BASE ADDRESS and how its used?
- How the presence of a DMA affects the interface logic?
- Designing the I/O and memory map for a microprocessor based system.
- Decoding the cpu’s control signals and address bus to generate enable signals.
- How these enable signals are used to interface a CPU with peripherals?
- How is conflict avoided between peripherals, system memory and display memory, etc?
- Generation of the READY signal for a CPU and insertion of WAIT STATES.
- What are WAIT STATES and why/when are they used?
- How is conflict avoided when CPU and display controller write to VRAM?
- What is ment by a ‘PAGE’ of display memory?
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