Associated with CDAC-ATC, Mumbai. Home | VC++ | VLSI Kits | Training | IP Cores | SOPC Cores | Turnkey Projects | About Us Training >> Training Courses >> VHDL >> A2.1 Training   • Training Courses     • VHDL     • ORCAD     • AUTOCAD     • PIC Microcontroller     • Assembly Language     • Linux & VC     • Others     • Process Logic Controller • Training Facilities   Projects implemented on an actual FPGA during the course and are implemented on our VLSI TRAINER KIT. COURSE A2.1: INTRODUCTION TO VERILOG AND VLSI DESIGN (II) PREREQUISITES Course A1.1: Introduction to VERILOG and VLSI design (I). CONTENTS 1. Timing and Delays Types of delay Models Path Delay Modeling Timing Checks Delay Back-Annotation 2. Switch-Level Modeling MOS Switches CMOS Switches Bi-directional Switches Power and Ground 3. User-Defined Primitives UDP basics Combinational UDPs Sequential UDPs 4. Programming Language Interface Uses of PLI Linking of Invocation of PLI Tasks Internal Data Representation PLI Library Routines 5. Logic Synthesis with Verilog HDL What is Logic Synthesis Impact of Logic Synthesis Verilog HDL Synthesis Synthesis Design Flow Projects Implemented on an actual FPGA during the Course Parametric designing of:         1. Mux         2. Encoder         3. Decoder         4. Priority Encoder         5. Half Adder/Full Adder/4-bit Adder         6. Comparator         7. Counter         8. Shift Register © 2008 System Automation Group Home | VC++ | VLSI Kits | Training | IP Cores | SOPC Cores | Turnkey Projects | About Us