System Automation Group

Associated with CDAC-ATC, Mumbai.

Training >> Training Courses >> VHDL >> A16

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The above VLSI components will be designed in VHDL and simulated on the MAXPLUS+2 software from ALTERA inc. The design will then be implemented on the VLSI design kit.

COURSE A16: FIR,IIR FILTERS

USES

Filteration of analog data for digital control systems, from sensors such as-
pH, pressure, temperature, gas, voltage, current, flow rate etc, digital filters as in mobile telephony

PREREQUISITES

        Course A14. FIFO buffers
        Course-A1. Introduction to VHDL and VLSI design (I)

CONTENTS

        1. Filter architecture
        2. Implementing digital math (adders,subtractors.multipliers)
        3. Generating the coefficients.
        4. Implementing the FIFO buffer.
        5. Designing the filter
        6. Observing filter o/p given a digital FM signal.
        7. Observing the D to A converted o/p