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COURSE A1: INTRODUCTION TO VHDL AND VLSI DESIGN (I)
PREREQUISITES
1. Knowledge of analog and digital electronics
CONTENTS
1. Introduction to Graphic Editor
2. Introduction to
- PLD's
- HDL's
- VHDL Design Entity
- Data Object
3. Signal Assignment Statement
- Concurrent Signal Assignment Statement
- Conditional Signal Assignment Statement
- Selected Signal Assignment Statement
4. Sequential Statements
- Process Statement
- IF Statement
- CASE Statement
- Using VARIABLE in Process
- Using a Process for a Combinational Circuit
5. Packages and Use Clauses
6. Components
7. Sequential Circuits
- Gated D Latch
- D,JK,T Flip Flop with CLR, PRN, ENB
- Using WAIT UNTIL Statement
- Flip Flops with Asynchronous / Synchronous Load
- Array of Flip - Flops
- Instantiating a Flip Flop from a Library
- Up/Down Counter
- Synchronous clear, load, enable Counter
- Modulus 200 up counter
- Shift Registers(4 – Bit)
8. Subprograms
9. Clock Configuration Guidelines
10. Metastability
11. Projects Implemented on an actual FPGA during the Course
- Mux(2:1, 4:1, 8:1, 16:1)
- Encoder(4:2, 8:3)
- Decoder(2:4, 3:8)
- Priority Encoder(4:2, 8:3)
- Half Adder / Full Adder / 4 – bit Adder
- Comparator(1 – Bit, 4 – Bit)
- Counter
- Shift Register
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